1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a static random access memory (SRAM) having static memory cells.
2. Description of the Related Art
In a system large-scale integrated circuit (LSI), memories having various memory capacities, word numbers and bit numbers are used. In the memories, SRAM macros prepared to permit memory macros with desired configurations to be formed by use of common unit blocks are used.
In the above SRAM macro, complementary data transferred from an SRAM cell to a bit line pair is amplified by use of a sense amplifier and output to the exterior. For example, as the sense amplifier, a synchronous type sense amplifier is used to attain a high-speed operation. The synchronous type sense amplifier amplifies data with minute amplitude in synchronism with a sense amplifier activation signal SAE.
Therefore, it is desirable to set the SAE timing as early as possible to attain the high-speed operation, but if the signal SAE is activated too early, an input potential difference supplied from the bit line pair to the sense amplifier does not become sufficiently large and the SRAM is erroneously operated. Therefore, it is important to set optimum SAE timing for the high-speed operation.
However, since the bit line delay and word line delay are changed accordingly if the bit line length, word line length and the like are changed, the optimum SAE timing is changed according to the macro configuration. In order to cope with the above problem, a method for generating a signal SAE by use of dummy cells, dummy word line and dummy bit line is used (reference document: Kenichi Osada et al., “Universal-Vdd 0.65-2.0V 32 kB Cache using Voltage-Adapted Timing-Generation Scheme and a Lithographical-Symmetric Cell”, 2001 ISSCC (International Solid-State Circuits Conference)/SESSION 11/SRAM 11.1).
The problem of the conventional timing generation method lies in the fact that the SRAM macro cannot be operated by use of power supply potentials of a wide range. When the power supply potential is gradually lowered, the data path delay rapidly becomes longer than the dummy bit line delay. The dummy bit line delay is a time period from the time the dummy word line potential is set to a high level until the potential of the dummy bit line swings to the threshold voltage (for example, approximately VDD/2) of the inverter circuit. Further, the data path delay is a time period from the time the word line potential is set to a high level until a potential difference (for example, approximately 100 mV) which can be sensed by the sense amplifier appears between the paired bit lines.
Therefore, the input potential difference at the sense amplifier activation time is more reduced as the power supply potential becomes lower. Since the minimum input potential difference required for the sense operation is caused by input offset voltage or the like of the sense amplifier due to a fluctuation in the manufacturing process, it is kept substantially constant even if the power supply potential becomes low. Therefore, if the input potential difference is reduced when the power supply potential is set at the low level, an erroneous operation occurs. If the dummy bit line delay is made longer in order to prevent occurrence of the erroneous operation when the power supply potential is set at the low level, the operation speed when the power supply potential is set at the high level is lowered.
Thus, with the conventional timing generation method, there occurs a problem that the SRAM macro cannot be operated by use of power supply potentials of a wide range without degrading the operation speed.